Job Summary: 4+ years of experience in Timing Analysis both at block level and SoC level Should have worked on Constraints development , Timing analysis DFT mode timing experience is preferred Hands on scripting skills on TCL...

Requirements: Digital Micro - architecture of complex IP and / or ASIC blocks Experience creating Verilog based designs from Scratch Experience developing AXI based IPs / Blocks Good Lint / CDC / Synthesis check experienc...