Job Description
Summary:
Under general supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chips.
Experience: 5 to 8 Years Job Location: Pune/Hyderabad
Skills required: In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes.
Should have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency.
Must have hands-on experience on PnR Suite from Synopsys/Cadence (Innovus, ICC2)
Strong experience on Static Timing Analysis (PrimeTime - SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre).
Understanding the practical application of methodologies and Physical Design Tools, Flow Automation and Improvements.
Experience in complex SOC integration, Low Power and High Speed Design and Advanced Physical Verification Techniques.
Employement Category:
Employement Type: Full time
Industry: IT
Functional Area: IT
Role Category: Hardware Design Technical Leader
Role/Responsibilies: Physical Design Technical Lead
Contact Details:
Company: Career Axes
Location(s): Hyderabad
Keyskills:
Physical Design Technical Lead
floorplanning
Power Grid Design
Placemen
CTS
Sta
Power Integrity Analysis
Physical Verification
Chip finishing
Tk