Memory Verification Engineer - Hyderabad
- Incise Infotech
- 3 - 8 years
- Hyderabad
- 4 years ago
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Job Description
- Hands-on experience in developing/understanding building block schematics, memory schematics, running circuit simulation with spice simulators, DC analysis, transient analysis.
- Experience in deciphering circuit behavior from schematics.
- Familiarity with circuit characterization, timing libraries.
- Experience in Verilog MOS switch level models and netlist simulation with zero delay, unit delay, and path delay simulations.
- Familiarity with static timing analysis
- Hands-on experience in Gate level simulations with SDF back annotation.
- Debug SDF annotation issues and ensure good annotation coverage.
- Hands-on experience with latch based designs and their timing requirements.
- Hands-on experience of System Verilog Assertions to specify expected design behavior
- Familiarity with UVM is a plus
- Strong communication skills, with the ability to convey complex technical concepts to other design peers in verbal and written form
Interested share resume to Sh*******i@in***e.in
Job Classification
Industry: Electronic Components / SemiconductorsFunctional Area: Other, Role Category: OtherRole: OtherEmployement Type: Full timeEducation
Under Graduation: B.Tech/B.E. in Any SpecializationPost Graduation: M.Tech in Electronics/TelecommunicationContact Details:
Company: Incise InfotechAddress: Noida, Uttar Pradesh, IndiaLocation(s): Hyderabad
Keyskills: Verilog memory schematics GLS System Verilog
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