The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc . The candidate will also be responsible for block level physical design closure in terms of timing, power, DRC/LVS etc.
REQUIREMENTS:
5-8 years of experience in ASIC Physical Design
Have good knowledge of entire physical design process from floorplan till GDS generation
Good Exposure to Physical Verification Process
Have hands-on experience in latest sub-micron technologies below 10 nm
Hands on experience in leading PnR tools Synopsys ICC/ICC2
Experience in low power designs and handling congestion or timing critical tiles will be preferred
Should be a quick learner and have good attention to detail
Experience in ECO implementation preferred
Scripting skills in Perl/Tcl/Python etc
Must have good communication & problem-solving skills.
Should be able to handle PnR tasks with minimal supervision

Keyskills: soc clock tree routing drc lvs floorplanning
Magna Infotech is a division of USD 400 + million Quess Group (quesscorp.com) which in turn is a subsidiary of USD 37+ billion - Canadian Multinational, Fairfax Financial Holding Group. Magna Infotech is the largest staff Augmentation and Solutions Company in India, USA and APAC regions. We are a ...