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Excellent opportunity For Senior Design Verification Engineers & Leads @ Capgemini

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 Excellent opportunity For Senior Design Verification Engineers & Leads

Job Description

Job Description:

Location: Bangalore, Hyderabad & Chennai


  • 5-14years of experience in verification & Soc & System verilog,UVM
  • You will be part of the team verifying IPs and SoCs leading to first Si success.
  • Manage and lead a team of Verification engineers
  • IP verification is coverage driven using latest industry standard methodologies and HVLs.
  • Work involves defining verification strategy, writing test plans, developing efficient test benches and test cases.
  • Code coverage, Functional coverage and assertions are desired.
  • ARM based SoC verification experience is an added advantage.
  • Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc. is a great plus.
  • Multiple positions with emphasis on AMS and Power aware verification.

Job Classification

Industry: Electronic Components / Semiconductors
Functional Area / Department: Production, Manufacturing & Engineering
Role Category: Engineering
Role: Engineering - Other
Employement Type: Full time

Contact Details:

Company: Capgemini
Location(s): Hyderabad

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Keyskills:   SOC Verification ARM UVM System Verilog

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₹ 50,000-3 Lacs P.A

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