Design and Verification Engineer Lead
- Capgemini
- 7 - 12 years
- Bengaluru
- 8 days ago
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Job Description
Job Summary
We are seeking an experienced Design Verification Engineer to be part of a highperformance team responsible for IP and SoC verification, driving firstsilicon success. The role involves defining verification strategies, leading verification teams, and executing coveragedriven verification using industrystandard methodologies such as SystemVerilog and UVM. Candidates with experience in ARM-based SoC verification, AMS, poweraware verification, and gatelevel simulation (GLS) will have a strong advantage.
Key Responsibilities
- Lead and execute IP and SoC level verification activities to ensure robust and defectfree silicon.
- Manage and mentor a team of Verification Engineers, providing technical guidance and project oversight.
- Define verification strategies and develop comprehensive verification plans aligned with product requirements.
- Architect and implement efficient SystemVerilog/UVMbased testbenches and verification environments.
- Develop and execute directed and constrainedrandom test cases to achieve coverage goals.
- Drive coveragedriven verification, including functional coverage, code coverage, and assertionbased verification (ABV).
- Perform and analyze GateLevel Simulations (GLS) for timing and logical correctness.
- Collaborate closely with design, architecture, and validation teams to ensure smooth verification closure.
- Contribute to continuous improvement of verification methodologies, tools, and best practices.
Technical Skills & Qualifications
Mandatory Skills
- 512 years of experience in Design Verification for IPs and SoCs.
- Strong expertise in SystemVerilog, UVM, and industrystandard verification methodologies.
- Handson experience in coveragedriven verification.
- Proficiency in functional coverage, code coverage, and assertions.
- Experience working with GateLevel Simulation (GLS).
- Solid understanding of digital design concepts and verification flows.
Preferred / Added Advantages
- ARMbased SoC verification experience.
- Exposure to AMS (Analog Mixed Signal) verification.
- Experience with poweraware verification techniques (UPF/CPF).
- Proficiency in at least one scripting language such as Perl, Python, C++, Unix Shell scripting, Makefiles, etc.
- Familiarity with simulation, coverage, and debugging tools in a Linux/Unix environment.
Leadership & Soft Skills
- Proven ability to lead and manage verification teams.
- Strong analytical and debugging skills for complex systemlevel issues.
- Excellent communication and collaboration skills across crossfunctional teams.
- Ability to drive projects independently and deliver within aggressive schedules.
Why Join Us
- Work on cuttingedge IP and SoC designs leading to firstsilicon success.
- Opportunity to lead and influence verification strategy at scale.
- Exposure to advanced verification technologies including UVM, AMS, GLS, and poweraware flows.
- Collaborative, innovationdriven engineering environment.
Job Classification
Industry: IT Services & ConsultingFunctional Area / Department: OtherRole Category: OtherRole: OtherEmployement Type: Full timeContact Details:
Company: CapgeminiLocation(s): Bengaluru
Keyskills: Design Verification SOC Verification UVM System Verilog
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