Rtl Engineer
- People Tech
- 5 - 8 years
- Hyderabad
- 11 days ago
- Email to a friend
- Report this job
Job Description
Job Title: RTL Design Engineer IP Development
Experience: 57 Years
Location: Hyderabad
Education: Bachelors / masters degree in ECE, CSE, or EEE
Job Summary
We are seeking an experienced RTL Design Engineer with strong expertise in IP development for embedded and FPGA-based systems. The ideal candidate will have hands-on experience in RTL design, AXI bus protocols, and Xilinx FPGA tool flows. This role requires strong architecture, design, and debugging skills, along with the ability to work independently and deliver high-quality solutions with minimal supervision.
Key Responsibilities
- Design and develop high-quality RTL (SystemVerilog/Verilog) for reusable IP blocks.
- Gather and analyze requirements, understand specifications, and define micro-architecture.
- Implement, verify, and debug RTL designs to meet performance, area, and timing goals.
- Perform architecture trade-off analysis to optimize performance and silicon area.
- Work with AXI bus protocols and embedded system interfaces.
- Execute logic synthesis and timing closure activities.
- Utilize Xilinx FPGA platforms and tool chains for implementation and validation.
- Collaborate with cross-functional teams while taking ownership of deliverables.
- Ensure designs are robust, scalable, and compliant with project standards.
Required Skills & Qualifications
- Strong experience in RTL design using SystemVerilog/Verilog.
- Proficiency in logic synthesis and timing closure.
- Solid understanding of AXI bus protocols and embedded systems.
- Hands-on experience with Xilinx FPGAs and Vivado / Vitis tool flows.
- Strong debugging, problem-solving, and analytical skills.
- Experience in architecture definition and performance/area optimization.
- Ability to work independently and deliver with minimal guidance.
Job Classification
Industry: IT Services & ConsultingFunctional Area / Department: Engineering - Hardware & NetworksRole Category: HardwareRole: ASIC / RTL / Logic Design EngineerEmployement Type: Full timeContact Details:
Company: People TechLocation(s): Hyderabad
Keyskills: Synthesis FPGA Timing Closure RTL Debugging Xilinx
Similar positions
Job Listings
We are in open beta version of website, please let us know if any issues, at: info(at)indigojobs.in