RTL Design Engineer (ASIC)
- Experis
- 4 - 9 years
- Hyderabad
- 21 days ago
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Job Description
Hi, Greetings from Experis IT! We are happy to shortlist your candidature for an interview with one of our leading IT clients eInfochips. Please find the details below: Position: RTL Design Engineer (ASIC)Company: eInfochipsJob Type: Permanent Location: Bangalore / Hyderabad / Noida / PuneExperience: 4+ Years
Job Summary:We are looking for a highly skilled RTL Design Engineer with strong experience in ASIC design and RTL coding. The ideal candidate will be responsible for developing high-quality RTL designs, working closely with architecture, verification, and physical design teams to deliver robust and optimized ASIC solutions.
Key Responsibilities:Develop and implement RTL design using Verilog/SystemVerilog for ASIC projects.Work closely with architecture teams to understand design specifications and translate them into RTL implementations.Perform design analysis, debugging, and optimization to meet performance, power, and area requirements.Collaborate with verification teams to support testbench development and resolve functional issues.Participate in design reviews, code reviews, and technical discussions.Support synthesis, linting, and CDC/RDC checks to ensure high-quality RTL.Work with physical design teams for timing closure and design implementation.Ensure adherence to design methodologies and coding guidelines.
Required Skills:
- Strong RTL coding expertise in Verilog/SystemVerilog.
- Experience in ASIC design and development flow.
- Knowledge of synthesis, timing analysis, and low-power design concepts.
- Familiarity with EDA tools (Synopsys, Cadence, or equivalent).
- Understanding of lint, CDC, and static analysis tools.
- Strong debugging and problem-solving skills.
Preferred Skills:
- Experience with UPF and low-power design methodologies.
- Knowledge of SoC design architecture.
- Experience working with ASIC verification teams.
- Exposure to FPGA prototyping is a plus.
Qualifications:
- Bachelors or Masters degree in Electronics, Electrical Engineering, VLSI, or related field.
Experience:
- Typically 3+ years of experience in RTL design for ASIC projects.
Job Classification
Industry: IT Services & ConsultingFunctional Area / Department: Engineering - Software & QARole Category: Software DevelopmentRole: Software Development - OtherEmployement Type: Full timeContact Details:
Company: ExperisLocation(s): Hyderabad
Keyskills: Verilog ASIC Design RTL Design SystemVerilog STA Low Power Design Synthesis CDC SoC Lint UPF
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