Greeting form Globex Digital.!
JD: Senior ASIC RTL Engineer
Experience: 5y-20y Years
Mode: FTE / Full time
Location: Bangalore, Hyderabad, Kochi Any Location
NP: Immediate-90days
Roles and Responsibility:
Senior ASIC/SoC RTL Engineer/Lead
Role : ASIC RTL Engineer / Digital Design
Mandatory Skill :
Good to have :
Details JD :
Expertise in SoC subsystem/IP design
Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog
In depth knowledge on RTL quality checks (Lint, CDC)
Knowledge of synthesis and low power is a plus
Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)
Good understanding of timing concepts
Knowledge of one or more of the interface protocols
Expertise in setting up and using tools like
Understanding of scripting languages like Make flow, Perl ,shell, python etc
Understanding of processor architecture and/or ARM debug architecture is a plus
Able to help and debug issues for multiple subsystems
Able to create/review design documents for multiple subsystems
Able to support physical design, verification, DFT and SW teams on design queries and reviews
interested Candidate Can forward their Profile, hidden_email, with following details,
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Keyskills: micro architecture rtl design amba ahb axi rtl coding spyglass
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