Senior Design Verification Engineer
- Einfochips
- 6 - 10 years
- Hyderabad
- 1 day ago
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Job Description
Job Title: Design Verification Engineer
Experience: 5+ Years
Location: Bangalore / Hyderabad / Chennai / Noida / Pune /
Ahmedabad (as applicable)
Job Description:
We are looking for an experienced Design Verification Engineer with 5+ years of strong hands-on experience in SoC/IP verification.
Key Responsibilities:
- Develop verification plans based on design specifications.
- Build and maintain SystemVerilog/UVM-based verification environments.
- Create test plans, test cases, and functional coverage models.
- Debug RTL issues and work closely with design teams to close coverage.
- Execute regression runs and analyze results.
- Ensure verification closure with high-quality standards.
Required Skills:
- Strong expertise in SystemVerilog and UVM
- Experience in SoC/IP level verification
- Good debugging skills in RTL and simulation failures
- Experience with functional coverage and assertions
- Familiarity with industry-standard simulators (VCS / Questa / Xcelium)
Preferred Skills (Any of the following):
- Experience in PCIe / DDR / AMBA (AXI/AHB/APB) / Ethernet / USB
- Exposure to emulation or FPGA prototyping
- Scripting knowledge in Python / Perl / Shell
Education:
B.E./B.Tech/M.E./M.Tech in Electronics / VLSI / Electrical Engineering or related field
Job Classification
Industry: Electronic Components / SemiconductorsFunctional Area / Department: Research & DevelopmentRole Category: Engineering & ManufacturingRole: Engineering & Manufacturing - OtherEmployement Type: Full timeContact Details:
Company: EinfochipsLocation(s): Hyderabad
Keyskills: Design Verification ASIC Verification Verilog SOC Verification UVM VLSI Design
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