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Memory Layout Engineer @ Capgemini

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Capgemini  Memory Layout Engineer

Job Description

Job Summary

Seeking a Memory Layout Design Engineer with hands-on experience in SRAM compiler layout, FinFET technologies, and advanced nodes (TSMC 3nm/2nm or Samsung equivalent), including exposure to RF memory.

Key Responsibilities

  • Design SRAM bitcell, periphery, and memory compiler layouts
  • Work on FinFET-based advanced nodes (3nm)
  • Ensure DRC/LVS closure and optimize PPA
  • Perform parasitic-aware layout design
  • Collaborate with circuit/design teams for full custom layout development
  • Support RF memory layout and signal integrity needs

Requirements

  • 3+ years in memory layout design
  • Strong expertise in SRAM & compiler layout
  • Experience with FinFET (TSMC/Samsung advanced nodes)
  • Tools: Cadence Virtuoso, Calibre (DRC/LVS/PEX)

Good to Have

  • RF memory experience
  • Scripting (SKILL/Python)
  • Knowledge of advanced lithography (EUV, multi-patterning)

Job Classification

Industry: IT Services & Consulting
Functional Area / Department: Other
Role Category: Other
Role: Other
Employement Type: Full time

Contact Details:

Company: Capgemini
Location(s): Bengaluru

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Keyskills:   Finfet Memory Design TSMC 3nm SRAM

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Capgemini

Capgemini Engineering combines, under one brand, a unique set of strengths from across the Capgemini Group: the world leading engineering and R&D services of Altran acquired by Capgemini in 2020 - and Capgemini's digital manufacturing expertise. With broad industry knowledge and cutting-edge ...

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