<?xml version="1.0" encoding="utf-8"?>
<rdf:RDF xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns="http://purl.org/rss/1.0/" xmlns:dc="http://purl.org/dc/elements/1.1/">
 <channel rdf:about="/rss.xml">
  <description>Latest jobs / Embedded, VLSI</description>
  <link>https://ineojobs.com/</link>
  <title>IneoJobs.com</title>
  <dc:date>12-04-2026</dc:date>
  <items>
   <rdf:Seq>
    <rdf:li rdf:resource="https://ineojobs.com/job/819750/rtl-design-engineer-at-globex-digital/"/>
    <rdf:li rdf:resource="https://ineojobs.com/job/818246/embedded-systems-engineer-at-diraa-hr-services/"/>
   </rdf:Seq>
  </items>
 </channel>
 <item rdf:about="https://ineojobs.com/job/819750/rtl-design-engineer-at-globex-digital/">
  <description>&lt;h4&gt;Job Description&lt;/h4&gt;&lt;ul&gt;&lt;span&gt;&lt;p&gt;Greeting form &lt;strong&gt;Globex Digital.!&lt;/strong&gt;&lt;/p&gt; &lt;p class=&quot;x_xmsonormal&quot;&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;&lt;strong&gt;JD: Senior&amp;nbsp;&lt;/strong&gt;&lt;strong&gt;ASIC RTL Engineer&lt;/strong&gt;&lt;/p&gt; &lt;p&gt;&lt;strong&gt;Experience: 5y-20y Years&lt;/strong&gt;&lt;/p&gt; &lt;p&gt;&lt;strong&gt;Mode: &lt;/strong&gt;&lt;strong&gt;FTE / Full time&lt;/strong&gt;&lt;/p&gt; &lt;p&gt;&lt;strong&gt;Location:&lt;/strong&gt; Bangalore, Hyderabad, Kochi Any Location&lt;/p&gt; &lt;p&gt;&lt;strong&gt;NP: Immediate-90days&lt;/strong&gt;&lt;/p&gt; &lt;p class=&quot;x_xmsonormal&quot;&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Roles and Responsibility&lt;/strong&gt;:&lt;/p&gt; &lt;p&gt;&lt;strong&gt;Senior ASIC/SoC RTL Engineer/Lead&lt;/strong&gt;&lt;/p&gt; &lt;p&gt;Role : ASIC RTL Engineer / Digital Design&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/p&gt; &lt;p&gt;Mandatory Skill :&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/p&gt; &lt;ul&gt; &lt;li&gt;&lt;strong&gt;RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory&lt;/strong&gt;&lt;/li&gt; &lt;li&gt;PCIe/DDR/Ethernet - Any One&lt;/li&gt; &lt;li&gt;I2C,UART/SPI&amp;nbsp; - Any One&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/li&gt; &lt;li&gt;Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One&lt;/li&gt; &lt;li&gt;Scripting languages like Make flow, Perl ,shell, python - Any One&lt;/li&gt; &lt;/ul&gt; &lt;p&gt;Good to have : &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/p&gt; &lt;ul&gt; &lt;li&gt;processor architecture / ARM debug architecture&lt;/li&gt; &lt;li&gt;debug issues for multiple subsystems&lt;/li&gt; &lt;li&gt;create/review design documents for multiple subsystems&lt;/li&gt; &lt;li&gt;Able to support physical design, verification, DFT and SW teams on design queries and reviews&lt;/li&gt; &lt;/ul&gt; &lt;p class=&quot;x_xmsonormal&quot;&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;Details JD :&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/p&gt; &lt;p&gt;Expertise in SoC subsystem/IP design&lt;/p&gt; &lt;p&gt;Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog&lt;/p&gt; &lt;p&gt;In depth knowledge on RTL quality checks (Lint, CDC)&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/p&gt; &lt;p&gt;Knowledge of synthesis and low power is a plus&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/p&gt; &lt;p&gt;Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)&amp;nbsp;&amp;nbsp;&lt;/p&gt; &lt;p&gt;Good understanding of timing concepts&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/p&gt; &lt;p&gt;Knowledge of one or more of the interface protocols&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/p&gt; &lt;ol&gt; &lt;li&gt;PCIe&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/li&gt; &lt;li&gt;DDR&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/li&gt; &lt;li&gt;Ethernet&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/li&gt; &lt;li&gt;I2C, UART, SPI&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/li&gt; &lt;/ol&gt; &lt;p&gt;Expertise in setting up and using tools like&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/p&gt; &lt;ol&gt; &lt;li&gt;Spyglass Lint/CDC &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/li&gt; &lt;li&gt;Synopsys DC&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/li&gt; &lt;li&gt;Verdi/Xcellium&amp;nbsp;&lt;/li&gt; &lt;/ol&gt; &lt;p&gt;Understanding of scripting languages like Make flow, Perl ,shell, python etc&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/p&gt; &lt;p&gt;Understanding of processor architecture and/or ARM debug architecture is a plus&lt;/p&gt; &lt;p&gt;Able to help and debug issues for multiple subsystems&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/p&gt; &lt;p&gt;Able to create/review design documents for multiple subsystems&amp;nbsp;&amp;nbsp;&lt;/p&gt; &lt;p&gt;Able to support physical design, verification, DFT and SW teams on design queries and reviews&amp;nbsp;&lt;/p&gt; &lt;p class=&quot;x_xmsonormal&quot;&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;&lt;strong&gt;interested Candidate Can forward their Profile, &lt;/strong&gt;&lt;strong&gt;&lt;em class=&quot;true-italic&quot;&gt;hidden_email&lt;/em&gt;,&lt;/strong&gt;&amp;nbsp;&lt;strong&gt;with following details,&lt;/strong&gt;&lt;/p&gt; &lt;p&gt;&lt;strong&gt;Please fill the Details below:&lt;/strong&gt;&lt;/p&gt; &lt;p&gt;Full Name&lt;/p&gt; &lt;p&gt;Contact Number&amp;nbsp;&lt;/p&gt; &lt;p&gt;Alternate Number&lt;/p&gt; &lt;p&gt;Email ID&lt;/p&gt; &lt;p&gt;Total Experience&lt;/p&gt; &lt;p&gt;Relevant Experience&lt;/p&gt; &lt;p&gt;Current CTC&lt;/p&gt; &lt;p&gt;Expected CTC&lt;/p&gt; &lt;p&gt;Offers&lt;/p&gt; &lt;p&gt;Notice Period/LWD&lt;/p&gt; &lt;p&gt;Reason for Change&lt;/p&gt; &lt;p&gt;Current Company&lt;/p&gt; &lt;p&gt;Pay Roll Company&lt;/p&gt; &lt;p&gt;LinkedIn&amp;nbsp;&lt;/p&gt; &lt;p&gt;Current Location&amp;nbsp;&lt;/p&gt; &lt;p&gt;Preferred Location&lt;/p&gt; &lt;p class=&quot;x_xmsonormal&quot;&gt;&amp;nbsp;&lt;/p&gt;&lt;/span&gt;&lt;/ul&gt;&lt;h4&gt;Employement Category:&lt;/h4&gt;&lt;b&gt;Employement Type: &lt;/b&gt;Full time&lt;/br&gt;&lt;b&gt;Industry: &lt;/b&gt;Semiconductors&lt;/br&gt;&lt;b&gt;Role Category: &lt;/b&gt;Embedded, VLSI&lt;/br&gt;&lt;b&gt;Functional Area: &lt;/b&gt;Not Specified&lt;/br&gt;&lt;b&gt;Role/Responsibilies: &lt;/b&gt;Rtl Design Engineer&lt;h4&gt;Contact Details:&lt;/h4&gt;&lt;b&gt;Company: &lt;/b&gt;Globex Digital&lt;/br&gt;&lt;b&gt;Location(s): &lt;/b&gt;Bengaluru&lt;/br&gt;&lt;b&gt;&lt;br /&gt;&lt;br /&gt;&lt;a href=&quot;https://ineojobs.com/job/819750/rtl-design-engineer-at-globex-digital/&quot;&gt;Apply&lt;/a&gt;&lt;br /&gt;</description>
  <link>https://ineojobs.com/job/819750/rtl-design-engineer-at-globex-digital/</link>
  <title>[Full Time] Rtl Design Engineer at Globex Digital</title>
  <dc:date>Tue, 07 Apr 2026 12:30:00 +0530</dc:date>
 </item>
 <item rdf:about="https://ineojobs.com/job/818246/embedded-systems-engineer-at-diraa-hr-services/">
  <description>&lt;h4&gt;Job Description&lt;/h4&gt;&lt;ul&gt;&lt;span&gt;&lt;p&gt;&lt;strong data-start=&quot;0&quot; data-end=&quot;21&quot;&gt;Embedded Keywords&lt;/strong&gt; are keywords that are &lt;strong data-start=&quot;44&quot; data-end=&quot;79&quot;&gt;naturally placed inside content&lt;/strong&gt; (like sentences, paragraphs, articles, or web pages) instead of being listed separately. They are mainly used in &lt;strong data-start=&quot;193&quot; data-end=&quot;229&quot;&gt;SEO (Search Engine Optimization)&lt;/strong&gt; to help search engines understand what a page is about.&lt;/p&gt;&lt;/span&gt;&lt;/ul&gt;&lt;h4&gt;Employement Category:&lt;/h4&gt;&lt;b&gt;Employement Type: &lt;/b&gt;Full time&lt;/br&gt;&lt;b&gt;Industry: &lt;/b&gt;Manufacturing&lt;/br&gt;&lt;b&gt;Role Category: &lt;/b&gt;Embedded, VLSI&lt;/br&gt;&lt;b&gt;Functional Area: &lt;/b&gt;Not Specified&lt;/br&gt;&lt;b&gt;Role/Responsibilies: &lt;/b&gt;Embedded Systems Engineer&lt;h4&gt;Contact Details:&lt;/h4&gt;&lt;b&gt;Company: &lt;/b&gt;Diraa Hr Services&lt;/br&gt;&lt;b&gt;Location(s): &lt;/b&gt;Chennai&lt;/br&gt;&lt;b&gt;&lt;br /&gt;&lt;br /&gt;&lt;a href=&quot;https://ineojobs.com/job/818246/embedded-systems-engineer-at-diraa-hr-services/&quot;&gt;Apply&lt;/a&gt;&lt;br /&gt;</description>
  <link>https://ineojobs.com/job/818246/embedded-systems-engineer-at-diraa-hr-services/</link>
  <title>[Full Time] Embedded Systems Engineer at Diraa HR Services</title>
  <dc:date>Thu, 26 Mar 2026 12:30:00 +0530</dc:date>
 </item>
</rdf:RDF>