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Senior Logic Design Engineer Cache () @ Kpr sugar apperals

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 Senior Logic Design Engineer Cache ()

Job Description

    Logic Design Lead - Chip Infrastructure and Security Fortune 100 Organization Location: Bangalore Logic Design Lead - Chip Infrastructure and Security Introduction As a Hardware Developer , youll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in todays market. Your Role and Responsibilities As a Logic design lead, you will be responsible for leading the design and development of the POR Boot Engine, Boot security features, and the test & debug infrastructure for very high performance Processor chips/ ASICs. You will be part of the design team which will deliver this critical infrastructure to Mainframe, POWER processors, and other ASICs. Lead the Development of features, present the proposed architecture in High level design discussions Required Technical and Professional Expertise 8 to 12 years of work experience in Architecture/ microarchitecture/ RTL Logic design of Test and Debug infrastructure for Processors/ SoCs Security architecture- Self Boot engine, Secure boot SPI, I2C, serial communication protocols, OTPROM, on-chip sensors Good understanding of clocks and reset architecture, low power design Proficient in HDLs- VHDL must/ Verilog Experience in working with architecture/ FW/ SW teams Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage Good understanding of Physical Design, and able to collaborate with physical design team for floor-planning, placement of blocks for achieving high-performance design Experience in leading uarch, RTL design for feature enhancements. Being a lead, ability - to quickly understand issues spanning multiple functional domains, switch context frequently, and provide solutions to problems, is necessary. * Preferred Technical And Professional Expertise Processor development experience Processor domain knowledge Contact: Uday Mulya Technologies hidden_email "Mining The Knowledge Community",

Employement Category:

Employement Type: Full time
Industry: IT - Hardware / Networking
Role Category: Not Specified
Functional Area: Not Specified
Role/Responsibilies: Senior Logic Design Engineer Cache ()

Contact Details:

Company: Mulya Technologies
Location(s): All India

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Keyskills:   Architecture Security architecture SPI I2C VHDL Verilog Verification Validation Physical Design Floorplanning Clocks Low power design

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Kpr sugar apperals

Kpr sugar and apperals ltd