Senior Design Verification Engineer
- Cyient
- 7 - 12 years
- Hyderabad
- 10 months ago
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Job Description
Lead /Senior Design Verification Engineer-GLS/UVM |Hyderabad, India | Experience:7-12 Years
Role Overview:
We are looking for an experienced and detail-oriented Design Verification Engineer with strong expertise in Gate-Level Simulation (GLS) and SystemVerilog/UVM methodology. The role involves validating complex SoC/IP designs in post-synthesis environments, working closely with design, DFT, and physical implementation teams. Experience with HBM (High Bandwidth Memory) is a strong advantage.
Key Responsibilities:
- Develop and maintain UVM-based verification environments for complex digital IP and SoCs.
- Plan and execute GLS (Gate-Level Simulation) flows including SDF annotation, X-checking, and timing-aware validation.
- Perform debug of timing-related and X-propagation issues at netlist level.
- Drive regression automation, simulation coverage analysis, and documentation of results.
- Work closely with cross-functional teams (DFT, synthesis, STA, PD) to resolve post-synthesis and post-layout issues.
- (Optional) Support validation of HBM interfaces, including protocol-level behavior and error scenarios.
Required Skills:
- 7-12 years of design verification experience in ASIC or SoC environments.
- Solid expertise in SystemVerilog, UVM, and assertion-based verification.
- Strong hands-on experience in GLS including:
- SDF annotation
- Debugging setup/hold, X issues
- Power-aware simulations (optional)
- Familiarity with simulation tools: VCS, Xcelium, Questa, Debussy/Verdi.
- Experience with scripting (Perl, Python, Shell) for automation.
- Good understanding of chip lifecycle from RTL to GDSII.
Nice to Have:
- Experience working with HBM protocols or memory controller verification.
- Exposure to low-power verification, UPF flows.
- Familiarity with post-silicon bring-up and debug is a plus.
Interested? Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034*** / Send your profile to ra**********m@cy***t.com
Job Classification
Industry: Electronic Components / SemiconductorsFunctional Area / Department: Research & DevelopmentRole Category: Engineering & ManufacturingRole: Design EngineerEmployement Type: Full timeContact Details:
Company: CyientLocation(s): Hyderabad
Keyskills: Design Verification Simulation UVM System Verilog Gls
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